verilog六选一扫描器

library IEEE;
entity kz is
  Port ( clk : in std_logic;
   en : in std_logic;
   a1 : in std_logic_vector(3 downto 0);
   a2: in std_logic_vector(3 downto 0);
a3: in std_logic_vector(3 downto 0);
a4: in std_logic_vector(3 downto 0);
a5 : in std_logic_vector(3 downto 0);
a6: in std_logic_vector(3 downto 0);
   d : out std_logic_vector(2 downto 0);
   q : out std_logic_vector(3 downto 0));
end kz;
architecture Behavioral of kz is
--SIGNAL A:std_logic_vector:="000";
SIGNAL A:std_logic_vector(2 downto 0);
begin
--SIGNAL A:std_logic_vector:="000";
process(clk)
begin
if(en='1') then
if(clk'event and clk='1') then
if (A="000") then
   q<=a1;

d<="000";
elsif (A="001") then
q<=a2;
  
d<="001";
elsif (A="010") then
q<=a3;
d<="010";
elsif (A="011") then
q<=a4;
d<="011";
elsif (A="100") then
q<=a5;

d<="100";
elsif (A="101") then
q<=a6;

d<="101";


end if;
end if;
end if;
A<=A+'1';
if (A="110")THEN
A<= "000";
END IF;
end process;
end Behavioral;

WARNING:Xst:819 - D:/socshiyan/r/test12/kz.vhdl line 29: The following signals are missing in the process sensitivity list:



d的功能是确定输出的值是第几位