verilog 设计8bit乘8bit硬件乘法器

verilog 设计8bit乘8bit硬件乘法器

如果仅仅是实现而不要求性能的话，这样一个乘法器并不难，而且网上应该也有很多相关的材料。<br>
搜索一下booth算法

缺乏自己查阅资料、思考问题的过程，很难帮你的

乘法器应该不是很难吧，网上例子很多的．<br>
你搜索verilog实例，应该有的．

module mul_ser (clk, x, a, y);&nbsp;&nbsp;//----&gt; Interface<br>
<br>
&nbsp;&nbsp;input&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;clk;<br>
&nbsp;&nbsp;input&nbsp;&nbsp;[7:0]&nbsp;&nbsp;x, a;<br>
&nbsp;&nbsp;output [15:0] y;<br>
&nbsp;&nbsp;reg&nbsp; &nbsp; [15:0] y;<br>
<br>
<br>
&nbsp;&nbsp;always @(posedge clk) //-&gt; Multiplier in behavioral style<br>
&nbsp;&nbsp;begin : States<br>
&nbsp; &nbsp; parameter s0=0, s1=1, s2=2;<br>
&nbsp; &nbsp; reg [2:0] count;<br>
&nbsp; &nbsp; reg [1:0] state;<br>
&nbsp; &nbsp; reg&nbsp;&nbsp;[15:0] p, t;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;// Double bit width<br>
&nbsp; &nbsp; reg&nbsp;&nbsp;[7:0] a_reg;<br>
&nbsp; &nbsp; case (state) <br>
&nbsp; &nbsp;&nbsp; &nbsp;s0 : begin&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;// Initialization step <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;a_reg &lt;= a;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;state &lt;= s1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;count = 0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;p &lt;= 0;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; // Product register reset<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;t &lt;= {{8{x[7]}},x}; // Set temporary shift register to x<br>
&nbsp; &nbsp;&nbsp; &nbsp;end&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; <br>
&nbsp; &nbsp;&nbsp; &nbsp;s1 : begin&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; // Processing step<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;if (count == 7)&nbsp; &nbsp;// Multiplication ready<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; state &lt;= s2;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;else&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; begin&nbsp; &nbsp;&nbsp; &nbsp;// not allow variable bit selects, <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; if (a_reg[0] == 1) // see (LRM Sec. 4.2.1)<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;p &lt;= p + t;&nbsp; &nbsp;&nbsp; &nbsp;// Add 2^k<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; a_reg &lt;= a_reg &gt;&gt; 1;// Use LSB for the bit select<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; t &lt;= t &lt;&lt; 1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; count = count + 1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; state &lt;= s1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;end<br>
&nbsp; &nbsp;&nbsp; &nbsp;end<br>
&nbsp; &nbsp;&nbsp; &nbsp;s2 : begin&nbsp; &nbsp;&nbsp; &nbsp; // Output of result to y and<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;y &lt;= p;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;// start next multiplication<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;state &lt;= s0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;end<br>
&nbsp; &nbsp; endcase&nbsp;&nbsp;<br>
&nbsp;&nbsp;end<br>
<br>
endmodule

直接让VHDL软件实现呀，直接用&ldquo;*&rdquo;就可以了，不过综合的时候在SINPLIFY中指定用&ldquo;LOGIC&rdquo;实现，就不会用到芯片的DSP IP核了

谢谢楼主分享~~~~~~~

可以直接调用IP核实现

期待好一点的算法！！

module mult_for(outcome,a,b);
parameter size=8;
input[size:1] a,b; //两个操作数
output[2*size:1] outcome; //结果
reg[2*size:1] outcome;
integer i;
always @(a or b)
begin
outcome=0;
for(i=1; i<=size; i=i+1) //for 语句
if(b[i]) outcome=outcome +(a << (i-1));
end
endmodule
这个程序看看还可以，如果仿真的话，会有很多毛刺