|
module count4(clk,reset,out,y);<br>
<br>
input clk;<br>
input reset;<br>
output [3:0] out;<br>
output y;<br>
<br>
reg [3:0] out;<br>
reg y;<br>
<br>
always @(posedge clk)<br>
begin<br>
if(!reset)<br>
out <= 4'b0;<br>
else <br>
out <= out + 1;<br>
end<br>
<br>
always @(negedge clk)<br>
begin<br>
if (out >= 4'b0100 && out <= 4'b1000)<br>
y = 1;<br>
else<br>
y=0;<br>
end<br>
<br>
endmodule |
|