这是什么原因？

module hz(t1,t2,t3,t4,t5,deng1,deng2,deng3,deng4,deng5);
input t1,t2,t3,t4,t5;
output deng1,deng2,deng3,deng4,deng5;
reg deng1,deng2,deng3,deng4,deng5;
reg k1,k2,k3,k4,k5;
initial
begin
k1=0;
#1000000000 forever begin
#1000000000 k1=~k1;
end
end
initial
begin
k2=0;
#1000000000 forever begin
#1000000000 k2=~k2;
end
end
initial
begin
k3=0;
#1000000000 forever begin
#1000000000 k3=~k3;
end
end
initial
begin
k4=0;
#1000000000 forever begin
#1000000000 k4=~k4;
end
end
initial
begin
k5=0;
#1000000000 forever begin
#1000000000 k5=~k5;
end
end

always begin
if(t1)
deng1=1;
else
deng1=k1;
end
always begin
if(t2)
deng2=1;
else
deng2=k2;
end
always begin
if(t3)
deng3=1;
else
deng3=k3;
end
always begin
if(t4)
deng4=1;
else
deng4=k4;
end
always begin
if(t5)
deng5=1;
else
deng5=k5;
end
endmodule






Error (10119): Verilog HDL Loop Statement error at Verilog1.v(20): loop with non-constant loop condition must terminate within 250 iterations

我用modelsim编译了一下，结果
Error:E:/modelsim_ase/examples/hz.v(14):"initial":ayntax error,unexpected"initial"