此为程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cal_test is
port (row ut std_logic_vector(3 downto 0);
col:in std_logic_vector(3 downto 0);
flhz:in std_logic;
rst:in std_logic;
c0 ut std_logic_vector(3 downto 0);
c1 ut std_logic_vector(3 downto 0);
c2 ut std_logic_vector(3 downto 0)
);
end cal_test;
architecture beh of cal_test is
type state_type is (s0,s1,s2,s3,s4);
signal state : state_type;
signal d,d0,d1,d2,d3,d_reg:std_logic_vector(4 downto 0);
signal op : std_logic_vector(1 downto 0);
signal a:std_logic_vector(7 downto 0);
signal datac, datal, datah:std_logic_vector(3 downto 0);
begin
d<=d0 or d1 or d2 or d3;
process(flhz, rst)
begin
if (rst='1') then
state<=s0;
datal<="0000";
datah<="1011";
datac<="1011";
row<="1110";
elsif (flhz' event and flhz='1') then
case state is
when s0=>
case col is
when "1110" => d0 <="10000";
when "1101" => d0 <="10100";
when "1011" => d0 <="11000";
when "0111" => d0 <="11100";
when others => d0 <="00000";
end case;
row<="1101";
state<=s1;
when s1=>
case col is
when "1110" => d1 <="10001";
when "1101" => d1 <="10101";
when "1011" => d1 <="11001";
when "0111" => d1 <="11101";
when others=> d1 <="00000";
end case;
state<=s2;
row<="1011";
when s2=>
case col is
when "1110" => d2 <="10010";
when "1101" => d2 <="10110";
when "1011" => d2 <="11010";
when "0111" => d2 <="11110";
when others=> d2 <="00000";
end case;
state<=s3;
row<="1011";
when s3=>state<=s4;
case col is
when "1110" => d3 <="10011";
when "1101" => d3 <="10111";
when "1011" => d3 <="11011";
when "0111" => d3 <="11111";
when others=> d3 <="00000";
end case;
when s4=> row <="1110";
state<=s0;
if (d/=d_reg) then
d_reg<=d;
if ((d<="11001") and (d>="10000"))then
datah<=datal;
datal<=d(3 downto 0);
elsif (d="11010") then
op<="01";
a<=datah&datal;
datah<="0000";
datal<="0000";
elsif (d="11011") then
op<="10";
a<=datah & datal;
datah<="0000";
datal<="0000";
elsif(d="11100") then
datal<="0000";
datah<="1011";
datac<="1011";
elsif (d="1111") then
case op is
when "01" =>if((a (3 downto 0)+datal)<="1001" and (a(3 downto 0)+datal) >=a(3 downto 0))
then
datal<=a(3 downto 0)+datal;
if((a (7 downto 4)+datah)<="1001" and (a(7 downto 4)+datah)>=a(7 downto 4))
then
datah<=a(7 downto 4)+datah;
datac<="0001";
else
datah<=a(7 downto 4)+datah;
datac<="0001";
end if;
else
datal<=a(3 downto 0)+datal+"0110";
if((a (7 downto 4)+datah+"0001"))<="1001" and (a(7 downto 4)+datah+"0001">a(7 downto 4)) then
datah<=a(7 downto 4)+datah+"0001";
datac<="1011";
else
datah<=a(7 downto 4)+datah+"0110"+"0001";
datac<="0001";
end if;
end if;
when "10"=> if(a<datah&datal) then
datac<="1010";
if (a (3 downto 0) >datal) then
datal<=datal+"1010"-a(3 downto 0);
datah<=datah-"0001"-a(7 downto 4);
else
datal<=datal-a(3 downto 0);
datah<=datah-a(7 downto 4);
end if;
else
datac<="1011";
if (a(3 downto 0)<datal) then
datal<=a(3 downto 0)+"1010"-datal;
datah<=a(7 downto 4 )-"0001"-datah;
else
datal<=a(3 downto 0)-datal;
datah<=a(7 downto 4)-datah;
end if;
end if;
when others=>null;
end case;
end if;
end if;
end case;
c0<=datal;
c1<=datah;
c2<=datac;
end if;
end process;
end beh;
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