[求助]verilog语法问题!!!!!!关于sha256计算~~~~~~~~~~~~~~~~

tj328111241 · 发表于 2013-4-25 16:15:13

以下是本人写的verilog模块,用于计算sha256中的一个块

维基百科的伪代码表述:
http://zh.wikipedia.org/wiki/SHA ... 4.E7.AE.97.E6.B3.95

编译器: ModelSim Se10.1a
编译环境: win xp sp3

提示错误:

** Error: E:\modeltech_10.1a\my project\sha-256-calcblock.v(115): near "genvar": syntax error, unexpected genvar
** Error: E:\modeltech_10.1a\my project\sha-256-calcblock.v(116): (vlog-2730) Undefined variable: 'i'.
** Error: E:\modeltech_10.1a\my project\sha-256-calcblock.v(116): near ")": syntax error, unexpected ')', expecting ';'
** Error: E:\modeltech_10.1a\my project\sha-256-calcblock.v(120): near "endgenerate": syntax error, unexpected endgenerate
** Error: E:\modeltech_10.1a\my project\sha-256-calcblock.v(123): near ")": syntax error, unexpected ')', expecting ';'
** Error: E:\modeltech_10.1a\my project\sha-256-calcblock.v(131): near "endgenerate": syntax error, unexpected endgenerate
** Error: E:\modeltech_10.1a\my project\sha-256-calcblock.v(144): near ")": syntax error, unexpected ')', expecting ';'
** Error: E:\modeltech_10.1a\my project\sha-256-calcblock.v(148): (vlog-2730) Undefined variable: 's0'.
** Error: E:\modeltech_10.1a\my project\sha-256-calcblock.v(149): near "maj": syntax error, unexpected IDENTIFIER, expecting ';'
** Error: E:\modeltech_10.1a\my project\sha-256-calcblock.v(189): (vlog-2730) Undefined variable: 'rightrotate_32bit'.
** Error: E:\modeltech_10.1a\my project\sha-256-calcblock.v(189): (vlog-2730) Undefined variable: 'n'.
** Error: E:\modeltech_10.1a\my project\sha-256-calcblock.v(189): (vlog-2730) Undefined variable: 'data'.
** Error: E:\modeltech_10.1a\my project\sha-256-calcblock.v(191): near "endfunction": syntax error, unexpected endfunction

复制代码

代码:

module sha256calcblock(input [512:0] w, output reg [256:0] hash);
reg [31:0] k256 [0:63];
reg [31:0] hh [0:7];
reg [31:0] ww [0:63];
initial
fork
k256[0] = 32'h428a2f98;
k256[1] = 32'h71374491;
k256[2] = 32'hb5c0fbcf;
k256[3] = 32'he9b5dba5;
k256[4] = 32'h3956c25b;
k256[5] = 32'h59f111f1;
k256[6] = 32'h923f82a4;
k256[7] = 32'hab1c5ed5;
k256[8] = 32'hd807aa98;
k256[9] = 32'h12835b01;
k256[10] = 32'h243185be;
k256[11] = 32'h550c7dc3;
k256[12] = 32'h72be5d74;
k256[13] = 32'h80deb1fe;
k256[14] = 32'h9bdc06a7;
k256[15] = 32'hc19bf174;
k256[16] = 32'he49b69c1;
k256[17] = 32'hefbe4786;
k256[18] = 32'h0fc19dc6;
k256[19] = 32'h240ca1cc;
k256[20] = 32'h2de92c6f;
k256[21] = 32'h4a7484aa;
k256[22] = 32'h5cb0a9dc;
k256[23] = 32'h76f988da;
k256[24] = 32'h983e5152;
k256[25] = 32'ha831c66d;
k256[26] = 32'hb00327c8;
k256[27] = 32'hbf597fc7;
k256[28] = 32'hc6e00bf3;
k256[29] = 32'hd5a79147;
k256[30] = 32'h06ca6351;
k256[31] = 32'h14292967;
k256[32] = 32'h27b70a85;
k256[33] = 32'h2e1b2138;
k256[34] = 32'h4d2c6dfc;
k256[35] = 32'h53380d13;
k256[36] = 32'h650a7354;
k256[37] = 32'h766a0abb;
k256[38] = 32'h81c2c92e;
k256[39] = 32'h92722c85;
k256[40] = 32'ha2bfe8a1;
k256[41] = 32'ha81a664b;
k256[42] = 32'hc24b8b70;
k256[43] = 32'hc76c51a3;
k256[44] = 32'hd192e819;
k256[45] = 32'hd6990624;
k256[46] = 32'hf40e3585;
k256[47] = 32'h106aa070;
k256[48] = 32'h19a4c116;
k256[49] = 32'h1e376c08;
k256[50] = 32'h2748774c;
k256[51] = 32'h34b0bcb5;
k256[52] = 32'h391c0cb3;
k256[53] = 32'h4ed8aa4a;
k256[54] = 32'h5b9cca4f;
k256[55] = 32'h682e6ff3;
k256[56] = 32'h748f82ee;
k256[57] = 32'h78a5636f;
k256[58] = 32'h84c87814;
k256[59] = 32'h8cc70208;
k256[60] = 32'h90befffa;
k256[61] = 32'ha4506ceb;
k256[62] = 32'hbef9a3f7;
k256[63] = 32'hc67178f2;
hh[0] = 32'h6a09e667;
hh[1] = 32'hbb67ae85;
hh[2] = 32'h3c6ef372;
hh[3] = 32'ha54ff53a;
hh[4] = 32'h510e527f;
hh[5] = 32'h9b05688c;
hh[6] = 32'h1f83d9ab;
hh[7] = 32'h5be0cd19;
join
reg [31:0] a;
reg [31:0] b;
reg [31:0] c;
reg [31:0] d;
reg [31:0] e;
reg [31:0] f;
reg [31:0] g;
reg [31:0] h;
always @(w)
begin
genvar i, s0, s1, maj, t1, t2, ch;
generate for(i = 0; i < 16 ; i = i + 1)
fork
ww[31:0] <= w[i * 32:i * 32 + 31];
join
endgenerate
generate for(i = 16; i < 63 ; i = i + 1)
fork
//s0 = rightrotate_32bit(ww[i-15] , 7) ^ rightrotate_32bit(ww[i-15] , 18) ^ (ww[i-15] >> 3);
//s1 = rightrotate_32bit(ww[i-2] , 17) ^ rightrotate_32bit(ww[i-2] , 19) ^ (ww[i-2] >> 10);
//ww = ww[i-16] + s0 + ww[i-7] + s1;
ww = ww[i-16] + rightrotate_32bit(ww[i-15] , 7) ^ rightrotate_32bit(ww[i-15] , 18) ^ (ww[i-15] >> 3) + ww[i-7] + rightrotate_32bit(ww[i-2] , 17) ^ rightrotate_32bit(ww[i-2] , 19) ^ (ww[i-2] >> 10);
join
endgenerate
fork
a = hh[0]
b = hh[1]
c = hh[2]
d = hh[3]
e = hh[4]
f = hh[5]
g = hh[6]
h = hh[7]
join
generate for(i = 0; i < 63 ; i = i + 1)
begin
fork
begin
s0 = rightrotate_32bit(a , 2) ^ rightrotate_32bit(a , 13) ^ rightrotate_32bit(a , 22)
maj = (a & b) ^ (a & c) ^ (b & c)
t2 = s0 + maj
end
begin
s1 = rightrotate_32bit(e , 6) ^ rightrotate_32bit(e , 11) ^ rightrotate_32bit(e , 25)
ch = (e & f) ^ ((~ e) & g)
t1 = h + s1 + ch + k + w
end
join
fork
h = g
g = f
f = e
e = d + t1
d = c
c = b
b = a
a = t1 + t2
join
end
endgenerate
fork
hh[0] = hh[0] + a
hh[1] = hh[1] + b
hh[2] = hh[2] + c
hh[3] = hh[3] + d
hh[4] = hh[4] + e
hh[5] = hh[5] + f
hh[6] = hh[6] + g
hh[7] = hh[7] + h
join
end
endmodule
function rightrotate_32bit(input [31:0] data, input [5:0] n);
begin
rightrotate_32bit = (data[(31 - n):0] << (32 - n)) | ( data >> n);
end
endfunction

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[求助]verilog语法问题!!!!!!关于sha256计算~~~~~~~~~~~~~~~~

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