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本帖最后由 fpgaw 于 2010-11-12 06:20 编辑
今天我尝试在quartus中进行综合。所以我从书中抄了下面的verilog代码(很简单,很基础),(项目和文件名都为fre_ctr):
module fre_ctr(rst,clk,load,count_en,count_clr);
output count_en,count_clr,load;
input rst,clk;
reg count_clr,load;
always @(posedge clk)
begin if(rst) begin count_en <= 0; load <= 1; end
else begin count_en <= ~count_en;
load <= ~count_en;
end
end
assign count_clr = ~clk&load;
endmodule
但编译出错:
Error (10137): Verilog HDL Procedural Assignment error at fre_ctr.v(6): object "count_en" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at fre_ctr.v(7): object "count_en" on left-hand side of assignment must have a variable data type
Error (10219): Verilog HDL Continuous Assignment error at fre_ctr.v(11): object "count_clr" on left-hand side of assignment must have a net type
我不知道我的代码错在哪里?希望大家指点!!
谢 |
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