|
module 4_4_key(row,lin,clk,reset,LED);
input clk;
input lin;
input reset;
output row;
output LED;
reg [3:0] row;
reg [3:0] lin;
reg [15:0] counter;
reg [7:0] LED;
reg clk_20ms;
reg [7:0] rowlin;
always@(posedge clk)
begin
if(reset)
begin
counter<=0;
clk_20ms<=0;
end
else
begin
if(counter==16'b1001_1100_0100_0000)
begin
clk_20ms<=1;
counter<=0;
end
else
begin
counter<=counter+1;
clk_20ms<=0;
end
end
end
assign rowlin = {row[3:0],lin[3:0]}; //将行值和列值输出
always@(posedge clk,negedge clk)
begin
row<=4'b0000;
lin<=4'b1111;
if(rowlin!=8'b0000_1111)
begin
LED<=8'b1111_0000;
end
end
endmodule
Error (10170): Verilog HDL syntax error at 4_4_key.v(1) near text "44"; expecting an identifier
这是报错,小弟最近新学FPGA,希望大家给些指导啊~~~!!!! |
|