求大神帮忙看看这个错误怎么改

程序：
LIBRARY altera_mf;
USE altera_mf.all;


ENTITY line_buffer IS
PORT
(
clock: IN STD_LOGIC ;
shiftin: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
shiftout: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
taps: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END line_buffer;




ARCHITECTURE SYN OF line_buffer IS


SIGNAL sub_wire0: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1: STD_LOGIC_VECTOR (23 DOWNTO 0);






COMPONENT altshift_taps
GENERIC (
lpm_hint: STRING;
lpm_type: STRING;
intended_device_family : STRING;
number_of_taps: NATURAL;
power_up_state: STRING;
tap_distance: NATURAL;
width: NATURAL
);
PORT (
clock: IN STD_LOGIC ;
shiftin: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
shiftout: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
taps: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END COMPONENT;


BEGIN
shiftout <= sub_wire0(7 DOWNTO 0);
taps <= sub_wire1(23 DOWNTO 0);


ALTSHIFT_TAPS_component : ALTSHIFT_TAPS
GENERIC MAP (
-- intended_device_family => "Cylone II",
lpm_hint => "RAM_BLOCK_TYPE=M4K",
lpm_type => "altshift_taps",
intended_device_family => "Cylone II",
number_of_taps => 3,
power_up_state => "CLEARED",
tap_distance => 640,
width => 8
)
PORT MAP (
clock => clock,
shiftin => shiftin,
shiftout => sub_wire0,
taps => sub_wire1
);
END SYN;

错误：
# ** Error: E:/modelsim/median_filter_test/Line_buffer.vhd(98): Bad default binding for component instance "altshift_taps_component : altshift_taps".
# (Component generic "intended_device_family" is not on the entity.)
# ** Warning: [1] E:/modelsim/median_filter_test/Line_buffer.vhd(98): (vopt-3473) Component instance "altshift_taps_component : altshift_taps" is not bound.