我编了个小代码,仿真时出现竞争与冒险问题。有何解决办法不?高手一般是如何处理竞争与冒险的
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
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entity myFullAdder4 is
port(a,b:in std_logic_vector(3 downto 0);
c0:in std_logic;
c4ut std_logic;
sut std_logic_vector(3 downto 0));
end myFullAdder4;
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architecture behavior of myFullAdder4 is
signal cc:std_logic_vector(3 downto 0);
signal ss:std_logic_vector(4 downto 0):="00000";
begin
cc<=(0=>c0,others=>'0');
ss<=('0'&a)+('0'&b)+('0'&cc);
s<=a + b + cc;
c4<=ss(4);
end behavior;