library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY contrg IS
PORT (
trg : IN std_logic;
rst : IN std_logic;
qo : OUT std_logic);
END contrg;
ARCHITECTURE arch OF contrg IS
SIGNAL count : std_logic_vector(2 DOWNTO 0);
SIGNAL q:std_logic:='0';
BEGIN
PROCESS(trg,rst)
BEGIN
IF rst='1' THEN count<="000";q<='0';
ELSIF trg 'event and trg='1' THEN
IF count<="101" THEN count<="000";q<='1';
ELSE count<=count+1;
END IF;
END IF;
qo<=q;
END PROCESS;
END arch;
是想在计数满5之后,输出给出高电平,可是波形仿真却达不到,请各位帮忙看问题出在哪里