我写了一段程序，实现输出延迟输入5个时钟周期，但不对，请高手帮忙

module gen_clk(inta,clk,outb);
input inta,clk;//intainta,,inta inta
output outb;
reg outb;
reg [3:0] count;
reg temp1,temp2,temp3,temp4;
initial
begin
count=0;
end
always@(posedge clk )begin
count<=count+1;
if(count==1)
begin
temp1<=inta;
end
else if(count==2)
begin
temp2<=temp1;
end
else if(count==3)
begin
temp3<=temp2;
end
else if(count==4)
begin
outb<=temp3;
end
end
endmodule

回复 1# polozpt


    搞定了，自己的基础还是不行啊