With the TimeQuest command report_net_timing, you can generate a report that details the net delays for specific nets or all nets in your design. A net corresponds to a cell’s output pin.
#Report net timing for an output pin of a register
report_net_timing [get_nets *reg*]
#Report net timing for the top 10 nets
report_net_timing –nworst_delay 10
The use of this design is governed by, and subject to, the terms and conditions of the Altera® Hardware Reference Design License Agreement.