求教：这个错误怎么改

这是一个ROM只读存储器的VHDL代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY rom24s10 IS
PORT(g1,g2:IN STD_LOGIC;
       adr:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      dout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY rom24s10;
ARCHITECTURE behav OF rom24s10 IS
SUBTYPE word IS STD_LOGIC_VECTOR(3 DOWNTO 0);
TYPE memory IS ARRAY(0 TO 255)OF word;
SIGNAL adr_in:INTEGER RANGE 0 TO 255;
BEGIN
PROCESS(g1,g2,adr)IS
        VARIABLE rom:memory;
        VARIABLE startup:BOOLEAN:=TRUE;
        VARIABLE i:line;
        VARIABLE j:INTEGER;
BEGIN
IF startup THEN
   FOR j IN rom'RANGE LOOP
     READline(romin,i);
     READ(i,rom(j));
   END LOOP;
   startup:=FALSE;
END IF;
adr_in<=CONV_INTEGER(adr);
IF(g1='1' AND g2='1')THEN
   dout<=rom(adr_in);
ELSE
   dout<="ZZZZ";
END IF;
END PROCESS;
END ARCHITECTURE behav;

是这行代码出错了   VARIABLE i:line;
错误显示是：object "line" is used but not declared