上面这个代码,怎么编译都不过,显示错误为
Error (10200): Verilog HDL Conditional Statement error at LEDa.v(65): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
但是我改成下面这样就编译通过了,
if(cnt < 5'd18)
begin
cnt <= cnt + 1;
if(cnt == 1)
init <= 1;
end
else cnt<=0;