为什么会产生锁存器？一个AD7663转换程序

为什么会产生锁存器？一个AD7663转换程序

请问我写的一个AD7663转换程序为什么会产生锁存器？而且仿真时wr_data1和wr_data2没有数据产生，我不太明白是什么原因，请大家帮忙解释一下，谢谢！

注:本程序按照要求用cnvst作为时钟信号。cnvst分频后的时钟频率为100KHZ。程序和警告如下：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity chengxuad is
port(p:in std_logic_vector(15 downto 0);---16位数据输入   
rst,rd,cs,cnvst,byte:in std_logic;
wr_data1,wr_data2
       
ut std_logic_vector(7 downto 0));
end chengxuad;
architecture Behavioral of chengxuad is
type state is(start,convert,read);  ---定义各状态的子类型
signal current_state,next_state:state;
signal reg:std_logic_vector(15 downto 0);
begin
process(rst)
begin
  if(rst='0') then
   current_state<=start;
  elsif(cnvst'event and cnvst='0') then
   current_state<=next_state;
  end if;
end process;
process(cnvst,current_state)
variable count:integer:=0;
begin
if (cnvst'event) and (cnvst='0')and (cnvst'last_value='1') then
  if cs<='0' then
   case current_state is
     when start=>
   if count<10000 then
  next_state<=start;
  elsif count<=40000 and count>=10000 and cnvst<='0' then
  next_state<=convert;
  end if;
when convert=>
  if (count>=20000 and count<=40000) or (count>40000
  and count<=50000 ) then
   next_state<=read;
      else next_state<=convert;
  end if;
when read=>
   if rd<='0' then
  reg<=p;
  next_state<=start;
  else next_state<=read;
  end if;
     when others=> next_state<=start;
  end case;
end if;
end if;
end process;
process(current_state)
begin
if current_state=read then
  if byte<='0' then
  wr_data1<=reg(15 downto 8);
  wr_data2<=reg(7 downto 0);
  elsif byte<='1' then
   wr_data1<=reg(7 downto 0);
   wr_data2<=reg(15 downto 8);
   end if;
end if;
end process;
end Behavioral;

警告入下：
ARNING:Xst:819 - C:/程序/chengxu/chengxu.vhd line 57: The following signals are missing in the process sensitivity list:
byte, reg<15>, reg<14>, reg<13>, reg<12>, reg<11>, reg<10>, reg<9>, reg<8>, reg<7>, reg<6>, reg<5>, reg<4>, reg<3>, reg<2>, reg<1>, reg<0>.
Entity <chengxuad> analyzed. Unit <chengxuad> generated.
WARNING:Xst:647 - Input <cs> is never used.
WARNING:Xst:647 - Input <p> is never used.
WARNING:Xst:647 - Input <rd> is never used.
WARNING:Xst:653 - Signal <reg> is used but never assigned. Tied to value 0000000000000000.
WARNING:Xst:653 - Signal <next_state> is used but never assigned. Tied to value 00.
WARNING:Xst:737 - Found 8-bit latch for signal <wr_data1>.
WARNING:Xst:737 - Found 8-bit latch for signal <wr_data2>.
WARNING:Xst:1291 - FF/Latch <0> is unconnected in block <current_state>.
WARNING:Xst:1710 - FF/Latch<wr_data1_5> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data2_5> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data2_7> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data2_6> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data2_0> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data2_1> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data2_2> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data2_3> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data2_4> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data1_7> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data1_6> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data1_0> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data1_1> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data1_2> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data1_3> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1293 - FF/Latch<current_state_1> is constant in block <chengxuad>.
WARNING:Xst:1710 - FF/Latch<wr_data1_4> (without init value) is constant in block <chengxuad>.
WARNING:Xst:1291 - FF/Latch <current_state_0> is unconnected in block <chengxuad>.

不在敏感向量列表里面<br>
当然就有latch,是常见的问题<br>
lz看看这个<br>
sensitivity list<br>
就晓得了.琢磨琢磨

不在敏感向量列表里面<br>
当然就有latch,是常见的问题<br>
lz看看这个<br>
sensitivity list<br>
就晓得了.琢磨琢磨