本帖最后由 fpgaw 于 2010-11-18 16:22 编辑
module bingcuanfan(clk,rst,a,b,c);
input clk;
input rst;
input a;
output [7:0]b;
output [2:0]c;
reg[7:0]temp;
reg [7:0]b;
reg [10:0]state;
//reg[10:0]nextstate;
parameter idle=11'b00000000001,st0=11'b00000000010,st1=11'b00000000100,st2=11'b00000001000,st3=11'b00000010000,st4=11'b00000100000,st5=11'b00001000000,
st6=11'b00010000000,st7=11'b00100000000,st8=11'b01000000000,st9=11'b10000000000;
assign c=3'b111;
always @(negedge clk)
begin
if(rst)
begin
state<=idle;
temp<=8'b0;
b<=8'b1;
end
elsebegin
case(state)
idle: state<=st0;
st0:begin
temp<={temp[6:0],a};
state<=st1;
end
st1:begin
temp<={temp[6:0],a};
state<=st2;
end
st2:begin
temp<={temp[6:0],a};
state<=st3;
end
st3:begin
temp<={temp[6:0],a};
state<=st4;
end
st4:begin
temp<={temp[6:0],a};
state<=st5;
end
st5:begin
temp<={temp[6:0],a};
state<=st6;
end
st6:begin
temp<={temp[6:0],a};
state<=st7;
end
st7:begin
temp<={temp[6:0],a};
state<=st8;
end
st8:begin
b<=temp;
state<=st9;
end
st9:begin
state<=idle;
end
default:begin
state<=idle;
b<=8'b1;
temp<=8'b0;
end
endcase
end
end
endmodule |