module count6(clk,reset,ena,out,cout);<br>
input clk,reset,ena;<br>
output[3:0] out; <br>
output cout;<br>
reg[3:0] out;<br>
reg cout;<br>
<br>
always @(posedge clk or posedge reset)<br>
begin<br>
if(reset) out='b0000;<br>
else if(ena)<br>
begin<br>
if(out<'b0101) out=out+1;<br>
else out='b0000;<br>
end<br>
if(out==5)out='b1;<br>
else cout='b0;<br>
end<br>
endmodule |