verilog问题,什麽是过程语句先导的过程块?怎摸改?

要放到alwyas块里。呵呵

设计的同时把实际电路想好了<br>
不但写的代码思路清晰，资源也节俭

推荐写法：<br>
module mux(<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;out,&nbsp; &nbsp;//一项一项分开写<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;a, <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;b, <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;select<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; );<br>
<br>
output&nbsp; &nbsp; out; //也分开写，要对齐<br>
input&nbsp; &nbsp;&nbsp; &nbsp; a;<br>
input&nbsp; &nbsp;&nbsp; &nbsp; b;<br>
input&nbsp; &nbsp;&nbsp; &nbsp; select;<br>
<br>
assign out = select ? b : a;<br>
<br>
endmodule <br>
<br>
如果写成always模式，不要加上begin...end，无效代码尽量不要加。不过这也是仁者见仁，智者见智

多谢高手的指点!又学习了。
       

最好还是用20楼，看起来比较简洁！而且有效1！

呵呵&nbsp;&nbsp;大家多帮助 呵呵

受教…学习中！！