entity xiaodou is
port(clk,input: in std_logic;
output: out std_logic);
end xiaodou;
architecture xiaodou_arc of xiaodou is
signal cp:std_logic;
signal count:integer range 0 to 3;
begin
process(clk)
begin
if(clk'event and clk='1') then 检测上升沿
if(input='1')then 如果有输入信号
if(count=3)then count<=count; 当计数达到3时,保持计数值不变
else count<=count+1; 当其小于3时,进行加1处理
end if;
if(count=2)then cp<='1'; 如果计数达到2,cp置1
else cp<='0'; 其余情况全部为0
end if;
else count<=0; 如果计数出现非法状况,进行清零复位
end if;
end if;
output<=cp; 信号输出
end process;
end xiaodou_arc