vhdl，verilog hdl 该选择哪种语言？

verilog更接近于C，VHDL从ADA演化过来的。

还是先用verilog吧，在中国的业界也开始流行了。

vhdl 比较严谨,可以做较大规模的系统

如果是搞IC设计的， 我觉的两种语言都要看一下，学一下，然后要有一种精通的，不过VHDL比较难学一点，VERILOG HDL比较好学点，相对地

从Verilog开始吧<br>
这个比较容易上手<br>
VHDL感觉短时间内精通还是有点难度的<br>
而且现在用Verilog的也比较多了

不过我先学习了vhdl的，上学的时候<br>
工作时都用verilog了

没有错的啊

是啊．数字电路太重要了．回去一定要好好学习．．

verilog 现在比较流行,综合的工具也比较多,系统级么，ALOGRITHEM,RTL,LOGIC,GATE级的设计,VHDL比较适合特大SYSTEN级的设计.

The first decision a design group is often faced with is deciding which language to use. As the author of this book, I faced the same dilemma. The answer is usually dictated by the individual&rsquo;s own knowledge <br>
or personal preference.<br>
<br>
I know both languages equally well. I work using both. I teach them both. When asked which one I prefer, I usually answer that I was asked the wrong question. The right question should be &ldquo;Which one do I hate the least?&rdquo; And the answer to that question is: &ldquo;the one I&rsquo;m not currently working with&rdquo;.<br>
<br>
When working in one language, you do not notice the things that are simple to describe or achieve in that language. Instead, younotice the frustrations and how it would be easy to do it if only you were using the other language.In my opinion, both languages are inadequate by themselves, especially for verification. They are both equally poor for synthesizeable description. Some things are easier to accomplish in one language than in the other. For a specific model, one language is better than the other: one language has features that better map to the functionality to be modeled. However, as a general rule, neither is better than the other.Verification techniques transcend the language used. VHDL and Verilog are only implementation vehicles. Both are used throughout<br>
the book. It is not to say that this book is bilingual: examples are<br>
shown in only one language. I trust that a VHDL-only or Verilogonly<br>
reader will be able to understand the example in the other language,<br>
even though the syntax is slightly different.<br>
Some sections are Verilog only. In my experience Verilog is a much<br>
abused language. It has the reputation for being easier to learn than<br>
VHDL, and to the extent that the learning curve is not as steep, it is<br>
true. However, both languages provide similar concepts: sequential<br>
statements, parallel constructs, structural constructs, and the illusion<br>
of parallelism.<br>
For both languages, these concepts must be learned. Because of its<br>
lax requirements, Verilog lulls the user into a false sense of security.<br>
The user believes that he or she knows the language because there<br>
are no syntax errors or because the simulation results appear to be<br>
correct. Over time, and as a design grows, race conditions and fragile<br>
code structures become apparent, forcing the user to learn these<br>
important concepts. Both languages have the same area under the<br>
learning curve. VHDL&rsquo;s is steeper but Verilog&rsquo;s goes on for much<br>
longer. Some sections in this book take the reader further down the<br>
Verilog learning curve.<br>
<br>
[ 本帖最后由 chenhongyi 于 2006-11-17 11:37 编辑 ]